Datasheet

• DFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected
• DFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is
detected
• DFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is
detected
• DFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKC bit is
detected
• DFLLRCS - DFLL48M Reference Clock has Stopped: A “0-to-1” transition on the
PCLKSR.DFLLRCS bit is detected
• BOD33RDY - BOD33 Ready: A “0-to-1” transition on the PCLKSR.BOD33RDY bit is detected
• BOD33DET - BOD33 Detection: A “0-to-1” transition on the PCLKSR.BOD33DET bit is detected.
This is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
• B33SRDY - BOD33 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B33SRDY bit is
detected
• BOD12RDY - BOD12 Ready: A “0-to-1” transition on the PCLKSR.BOD12RDY bit is detected
• BOD12DET - BOD12 Detection: A “0-to-1” transition on the PCLKSR.BOD12DET bit is detected
• B12SRDY - BOD12 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B12SRDY bit is
detected
• PLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted.
• PLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during
normal operation mode.
• PLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time
DPLLCTRLB.LTIME has elapsed since the start of the FDPLL96M.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or
the SYSCTRL is reset. See Interrupt Flag Status and Clear (INTFLAG) register for details on how to clear
interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined
interrupt request to the NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read
the INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector
Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
17.6.14 Synchronization
Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to
other clock domains. The status of this synchronization can be read from the Power and Clocks Status
register (PCLKSR). Before writing to any of the DFLL48M control registers, the user must check that the
DFLL Ready bit (PCLKSR.DFLLRDY) in PCLKSR is set to one. When this bit is set, the DFLL48M can be
configured and CLK_DFLL48M is ready to be used. Any write to any of the DFLL48M control registers
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 190