Datasheet

17.6.8.5 Reference Clock Switching

When a software operation requires reference clock switching, the normal operation is to disable the

FDPLL96M, modify the DPLLCTRLB.REFCLK to select the desired reference source and activate the

FDPLL96M again.

17.6.8.6 Loop Divider Ratio updates

The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed to modify the loop

divider ratio and the loop divider ratio fractional part when the FDPLL96M is enabled. At that time, the

DPLLSTATUS.LOCK bit is cleared and set again by hardware when the output frequency reached a

stable state. The DPLL Lock Fail bit in the Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK)

is set when a falling edge has been detected. The flag is cleared when the software write a one to the

interrupt flag bit location.

Figure 17-6. RATIOCTRL Register Update Operation

CKRx

LDR

LDRFRAC

CLK_FDPLL96M

mult0

mult1

LOCK

LOCKL

17.6.8.7 Digital Filter Selection

The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise

between stability and jitter. Nevertheless a software operation can override the filter setting using the

DPLLCTRLB.FILTER field. The DPLLCTRLB.LPEN field can be use to bypass the TDC module.

17.6.9 3.3V Brown-Out Detector Operation

The 3.3V BOD monitors the 3.3V VDDANA supply (BOD33). It supports continuous or sampling modes.

The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as

well as the enable/disable settings are loaded from Flash User Calibration at startup, and can be

overridden by writing to the corresponding BOD33 register bit groups.

17.6.9.1 3.3V Brown-Out Detector (BOD33)

The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the

brown-out threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The

BOD33 can generate either an interrupt or a reset when VDDANA crosses below the brown-out threshold

level. The BOD33 detection status can be read from the BOD33 Detection bit (PCLKSR.BOD33DET) in

the Power and Clocks Status register.

At start-up or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row.

Refer to NVM User Row Mapping for more details.