Datasheet
DFLL48M might lock at a frequency that is lower than the targeted frequency. It is recommended to
use a reference clock frequency of 32kHz or lower to avoid this issue for low target frequencies.
• The accuracy of the reference clock.
17.6.8 FDPLL96M – Fractional Digital Phase-Locked Loop Controller (DFLL96M)
17.6.8.1 Overview
The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked
Loop (DPLL). The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-
Digital Converter (TDC), a test mode controller, a Digitally Controlled Oscillator (DCO) and a PLL
controller. It also provides a fractional multiplier of frequency N between the input and output frequency.
The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference
clock are XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates
a clock divider. The selected clock must be configured and enabled before using the FDPLL96M. If the
GCLK is selected as reference clock, it must be configured and enabled in the Generic Clock Controller
before using the FDPLL96M. Refer to GCLK – Generic Clock Controller for details. If the GCLK_DPLL is
selected as the source for the CLK_FDPLL96M_REF, care must be taken to make sure the source for
this GCLK is within the valid frequency range for the FDPLL96M.
The XOSC source can be divided inside the FDPLL96M. The user must make sure that the
programmable clock divider and XOSC frequency provides a valid CLK_FDPLL96M_REF clock
frequency that meets the FDPLL96M input frequency range.
The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only
depends on the FDPLL96M internal control of the final clock gater CG.
The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used.
This clock must be configured and enabled in the Generic Clock Controller before using the FDPLL96M.
Refer to GCLK – Generic Clock Controller for details.
Table 17-3. Generic Clock Input for FDPLL96M
Generic Clock FDPLL96M
FDPLL96M 32kHz clock GCLK_DPLL_32K for internal lock timer
FDPLL96M GCLK_DPLL for CLK_FDPLL96M_REF
Related Links
15. GCLK - Generic Clock Controller
17.6.8.2 Block Diagram
Figure 17-2. FDPLL96M Block Diagram
TDC
Digital
Filter
DCO
÷N
XOSC32K
XOSC
CK
GCLK_DPLL
CLK_FDPLL96M
User
Interface
CLK_FDPLL96M_REF
GCLK_DPLL_32K
Divider
CG
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 184