Datasheet

interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the DFLL Reference Clock
Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set.
17.6.7.2 Additional Features
17.6.7.2.1 Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M
can be up to several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in
the DFLL48M locking mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a
chill cycle, during which the CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is
enabled by default, but can be disabled by writing a one to the DFLL Chill Cycle Disable bit
(DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles might double the lock time.
Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock
(QL), which is also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable
bit (DFLLCTRL.QLDIS) in the DFLL Control register. The Quick Lock might lead to a larger spread in the
output frequency than chill cycles, but the average output frequency is the same.
17.6.7.2.2 USB Clock Recovery Mode
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame
(SOF). This mode is enabled by writing a '1' to both the USB Clock Recovery Mode bit and the Mode bit
in DFLL Control register (DFLLCTRL.USBCRM and DFLLCTRL.MODE).
Note:  In USB Clock Recovery mode, the status bits of the DFLL in OSCCTRL.STATUS are determined
by the USB bus activity, and have no valid meaning.
The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the
selected generic clock reference. When the USB device is connected, a SOF will be sent every 1ms, thus
DFLLVAL.MUX bits should be written to 0xBB80 to obtain a 48MHz clock.
In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored, and the value stored in the
DFLLVAL.COARSE will be used as final Coarse Value. The COARSE calibration value can be loaded
from NVM OTP row by software. The locking procedure will also go instantaneously to the fine lock
search.
The DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock
phase. The DFLLCTRL.STABLE bit state is ignored, an auto jitter reduction mechanism is used instead.
17.6.7.2.3 Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After
Wake bit (DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will
be re-enabled and start running with the same configuration as before being disabled, even if the
reference clock is not available. The locks will not be lost. When the reference clock has restarted, the
Fine tracking will quickly compensate for any frequency drift during sleep if DFLLCTRL.STABLE is zero. If
DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will lose all its locks, and needs to
regain these through the full lock sequence.
17.6.7.2.4 Accuracy
There are three main factors that determine the accuracy of F
clkdfll48m
. These can be tuned to obtain
maximum accuracy when fine lock is achieved.
Fine resolution: The frequency step between two Fine values. This is relatively smaller for high
output frequencies.
Resolution of the measurement: If the resolution of the measured F
clkdfll48m
is low, i.e., the ratio
between the CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 183