Datasheet

17.6.7.1 Basic Operation
17.6.7.1.1 Open-Loop Operation
After any reset, the open-loop mode is selected. When operating in open-loop mode, the output
frequency of the DFLL48M will be determined by the values written to the DFLL Coarse Value bit group
and the DFLL Fine Value bit group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register.
Using "DFLL48M COARSE CAL" value from NVM Software Calibration Area Mapping in DFLL.COARSE
helps to output a frequency close to 48 MHz.
It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output
frequency of the DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use.
CLK_DFLL48M is ready to be used when PCLKSR.DFLLRDY is set after enabling the DFLL48M.
Related Links
10.3.2 NVM Software Calibration Area Mapping
17.6.7.1.2 Closed-Loop Operation
In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once
the multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be
correctly configured before closed-loop operation can be enabled. After enabling the DFLL48M, it must
be configured in the following way:
1. Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock
Channel 0 (GCLK_DFLL48M_REF). Refer to GCLK – Generic Clock Controller for details.
2. Select the maximum step size allowed in finding the Coarse and Fine values by writing the
appropriate values to the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups
(DFLLMUL.CSTEP and DFLLMUL.FSTEP) in the DFLL Multiplier register. A small step size will
ensure low overshoot on the output frequency, but will typically result in longer lock times. A high
value might give a large overshoot, but will typically provide faster locking. DFLLMUL.CSTEP and
DFLLMUL.FSTEP should not be higher than 50% of the maximum value of DFLLVAL.COARSE and
DFLLVAL.FINE, respectively.
3. Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL
Multiplier register. Care must be taken when choosing DFLLMUL.MUL so that the output frequency
does not exceed the maximum frequency of the DFLL.
4. Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in
the DFLL Control register.
The frequency of CLK_DFLL48M (F
clkdfll48m
) is given by:

clkdfll48
= DFLLMUL  MUL × 
clkdfll48mref
where F
clkdfll48mref
is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and
DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet
user specified frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency
tuner as a starting point for Coarse. Writing DFLLVAL.COARSE to a value close to the final value before
entering closed-loop mode will reduce the time needed to get a lock on Coarse.
Using "DFLL48M COARSE CAL" from NVM Software Calibration Area Mapping for DFLL.COARSE will
start DFLL with a frequency close to 48 MHz.
Following Software sequence should be followed while using the same.
1. load "DFLL48M COARSE CAL" from NVM User Row Mapping in DFLL.COARSE register
2. Set DFLLCTRL.BPLCKC bit
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 181