Datasheet

17.5.1 I/O Lines
I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user
configuration.
17.5.2 Power Management
The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running.
The SYSCTRL interrupts can be used to wake up the device from sleep modes. The events can trigger
other operations in the system without exiting sleep modes. Refer to PM – Power Manager on the
different sleep modes.
Related Links
16. PM – Power Manager
17.5.3 Clocks
The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock
Controller (GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M,
DFLL48M and FDPLL96M.
The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager,
and the default state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the
PM – Power Manager.
The clock used by BOD33 and BOD12 in sampled mode is asynchronous to the user interface clock
(CLK_SYSCTRL_APB). Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is
also asynchronous to the user interface clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes
to certain registers will require synchronization between the clock domains. Refer to 17.6.14
Synchronization for further details.
Related Links
16.6.2.6 Peripheral Clock Masking
17.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires
the Interrupt Controller to be configured first. Refer to Nested Vector Interrupt Controller for details.
Related Links
11.2 Nested Vector Interrupt Controller
17.5.5 Debug Operation
When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar,
improper operation or data loss may result during debugging.
If debugger cold-plugging is detected by the system, BOD33 and BOD12 resets will be masked. The
BOD resets keep running under hot-plugging. This allows to correct a BOD33 user level too high for the
available supply.
17.5.6 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Interrupt Flag Status and Clear register (INTFLAG)
SAM D21 Family
SYSCTRL – System Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 175