Datasheet

16.8.10 APBC Mask
Name: APBCMASK
Offset: 0x20
Reset: 0x00010000
Property: Write-Protected
Bit 31 30 29 28 27 26 25 24
TCC3
Access
R R R R R R R R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
AC1 I2S PTC DAC AC ADC
Access
R R R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 1
Bit 15 14 13 12 11 10 9 8
TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 24 – TCC3 TCC2 APB Clock Enable
Value Description
0
The APBC clock for the TCC3 is stopped
1
The APBC clock for the TCC3 is enabled
Bit 21 – AC1 AC1 APB Clock Enable
Value Description
0
The APBC clock for the AC1 is stopped
1
The APBC clock for the AC1 is enabled
Bit 20 – I2S I2S APB Clock Enable
Value Description
0
The APBC clock for the I2S is stopped
1
The APBC clock for the I2S is enabled
Bit 19 – PTC PTC APB Clock Enable
Value Description
0
The APBC clock for the PTC is stopped
1
The APBC clock for the PTC is enabled
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 164