Datasheet

16.8.5 APBB Clock Select
Name: APBBSEL
Offset: 0x0A
Reset: 0x00
Property: Write-Protected
Bit 7 6 5 4 3 2 1 0
APBBDIV[2:0]
Access
R/W R/W R/W
Reset 0 0 0
Bits 2:0 – APBBDIV[2:0] APBB Prescaler Selection
These bits define the division ratio of the APBB clock prescaler (2
n
).
APBBDIV[2:0] Name Description
0x0 DIV1 Divide by 1
0x1 DIV2 Divide by 2
0x2 DIV4 Divide by 4
0x3 DIV8 Divide by 8
0x4 DIV16 Divide by 16
0x5 DIV32 Divide by 32
0x6 DIV64 Divide by 64
0x7 DIV128 Divide by 128
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 156