Datasheet

16.7 Register Summary
Offset Name Bit Pos.
0x00 CTRL 7:0
0x01 SLEEP 7:0 IDLE[1:0]
0x02
...
0x07
Reserved
0x08 CPUSEL 7:0 CPUDIV[2:0]
0x09 APBASEL 7:0 APBADIV[2:0]
0x0A APBBSEL 7:0 APBBDIV[2:0]
0x0B APBCSEL 7:0 APBCDIV[2:0]
0x0C
...
0x13
Reserved
0x14 AHBMASK
7:0 USB DMAC NVMCTRL DSU HPB2 HPB1 HPB0
15:8
23:16
31:24
0x18 APBAMASK
7:0 EIC RTC WDT GCLK SYSCTRL PM PAC0
15:8
23:16
31:24
0x1C APBBMASK
7:0 USB DMAC PORT NVMCTRL DSU PAC1
15:8
23:16
31:24
0x20 APBCMASK
7:0 SERCOM5 SERCOM4 SERCOM3 SERCOM2 SERCOM1 SERCOM0 EVSYS PAC2
15:8 TC7 TC6 TC5 TC4 TC3 TCC2 TCC1 TCC0
23:16 AC1 I2S PTC DAC AC ADC
31:24 TCC3
0x24
...
0x33
Reserved
0x34 INTENCLR 7:0 CKRDY
0x35 INTENSET 7:0 CKRDY
0x36 INTFLAG 7:0 CKRDY
0x37 Reserved
0x38 RCAUSE 7:0 SYST WDT EXT BOD33 BOD12 POR
16.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 150