Datasheet

IDLE mode, the user must configure the IDLE mode configuration bit group and must write a zero
to the SCR.SLEEPDEEP bit.
• Exiting IDLE mode: The processor wakes the system up when it detects the occurrence of any
interrupt that is not masked in the NVIC Controller with sufficient priority to cause exception entry.
The system goes back to the ACTIVE mode. The CPU and affected modules are restarted.
16.6.2.8.2 STANDBY Mode
The STANDBY mode allows achieving very low power consumption.
In this mode, all clocks are stopped except those which are kept running if requested by a running
module or have the ONDEMAND bit set to zero. For example, the RTC can operate in STANDBY mode.
In this case, its Generic Clock clock source will also be enabled.
The regulator and the RAM operate in low-power mode.
A SLEEPONEXIT feature is also available.
• Entering STANDBY mode: This mode is entered by executing the WFI instruction with the
SCR.SLEEPDEEP bit of the CPU is written to 1.
• Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up
the system. For example, a module running on a Generic clock can trigger an interrupt. When the
enabled asynchronous wake-up event occurs and the system is woken up, the device will either
execute the interrupt service routine or continue the normal program execution according to the
Priority Mask Register (PRIMASK) configuration of the CPU.
16.6.3 SleepWalking
SleepWalking is the capability for a device to temporarily wake-up clocks for the peripheral to perform a
task without waking-up the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device
can either be awakened by an interrupt (from a peripheral involved in SleepWalking) or enter into
STANDBY sleep mode again.
In this device, SleepWalking is supported only on GCLK clocks by using the on-demand clock principle of
the clock sources. Refer to On-demand, Clock Requests for more details.
Related Links
14.6 On-demand, Clock Requests
16.6.4 DMA Operation
Not applicable.
16.6.5 Interrupts
The peripheral has the following interrupt sources:
• Clock Ready flag
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or
the peripheral is reset. An interrupt flag is cleared by writing a one to the corresponding bit in the
INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or one
common interrupt request line for all the interrupt sources. Refer to Nested Vector Interrupt Controller for
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 148