Datasheet

16.6.2.8 Sleep Mode Controller
Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode
register (SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be
used as argument to select the level of the sleep mode.
There are two main types of sleep mode:
• IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped,
depending on the IDLE argument. Regulator operates in normal mode.
• STANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set.
Regulator operates in low-power mode. Before entering standby mode the user must make sure
that a significant amount of clocks and peripherals are disabled, so that the voltage regulator is not
overloaded.
Table 16-3. Sleep Mode Entry and Exit Table
Mode Level Mode Entry Wake-Up Sources
IDLE 0 SCR.SLEEPDEEP = 0
SLEEP.IDLE=Level
WFI
Synchronous
(2)
(APB, AHB), asynchronous
(1)
1 Synchronous (APB), asynchronous
2 Asynchronous
STANDBY SCR.SLEEPDEEP = 1
WFI
Asynchronous
Note:
1. Asynchronous: interrupt generated on generic clock or external clock or external event.
2. Synchronous: interrupt generated on the APB clock.
Table 16-4. Sleep Mode Overview
Sleep
Mode
CPU
Clock
AHB
Clock
APB
Clock
Oscillators Main
Clock
Regulator
Mode
RAM
Mode
ONDEMAND = 0 ONDEMAND = 1
RUNSTDBY=0 RUNSTDBY=1 RUNSTDBY=0 RUNSTDBY=1
Idle 0 Stop Run Run Run Run Run if requested Run if requested Run Normal Normal
Idle 1 Stop Stop Run Run Run Run if requested Run if requested Run Normal Normal
Idle 2 Stop Stop Stop Run Run Run if requested Run if requested Run Normal Normal
Standby Stop Stop Stop Stop Run Stop Run if requested Stop Low power Low power
16.6.2.8.1 IDLE Mode
The IDLE modes allow power optimization with the fastest wake-up time.
The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules
and clock sources by configuring the SLEEP.IDLE bit group. The module will be halted regardless of the
bit settings of the mask registers in the Power Manager (PM.AHBMASK, PM.APBxMASK).
Regulator operates in normal mode.
• Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if
the SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will
also be entered when the CPU exits the lowest priority ISR. This mechanism can be useful for
applications that only require the processor to run when an interrupt occurs. Before entering the
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
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