Datasheet

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Peripheral Clock Default State
CLK_EIC_APB Enabled
CLK_PAC1_APB Enabled
CLK_DSU_APB Enabled
CLK_NVMCTRL_APB Enabled
CLK_PORT_APB Enabled
CLK_HMATRIX_APB Enabled
CLK_PAC2_APB Disabled
CLK_SERCOMx_APB Disabled
CLK_TCx_APB Disabled
CLK_ADC_APB Enabled
CLK_ACx_APB Disabled
CLK_DAC_APB Disabled
CLK_PTC_APB Disabled
CLK_USB_APB Enabled
CLK_DMAC_APB Enabled
CLK_TCCx_APB Disabled
CLK_I2S_APB Disabled
When the APB clock for a module is not provided its registers cannot be read or written. The module can
be re-enabled later by writing the corresponding mask bit to one.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will
have several mask bits.
Note: Clocks should only be switched off if it is certain that the module will not be used. Switching off the
clock for the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash
memory. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the
corresponding APBx bridge, will make it impossible to write the mask registers again. In this case, they
can only be re-enabled by a system reset.
16.6.2.7 Reset Controller
The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in
order to determine proper action.
There are two groups of reset sources:
• Power Reset: Resets caused by an electrical issue.
• User Reset: Resets caused by the application.
The table below lists the parts of the device that are reset, depending on the reset type.
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 145