Datasheet

Figure 16-2. Synchronous Clock Selection and Prescaler
Clock gate
Clock gate
Prescaler
Sleep Controller
Sleep mode
CLK_AHB
Clock gate
Clock gate
CLK_APBA
Clock gate
Clock gate
CLK_APBC
Clock gate
Clock gate
CLK_APBB
APBCDIV
APBBDIV
APBADIV
CLK_PERIPHERAL_AHB_0
CLK_PERIPHERAL_AHB_1
CLK_PERIPHERAL_AHB_n
CLK_PERIPHERAL_APBA_0
CLK_PERIPHERAL_APBA_1
CLK_PERIPHERAL_APBA_n
CLK_PERIPHERAL_APBB_0
CLK_PERIPHERAL_APBB_1
CLK_PERIPHERAL_APBB_n
CLK_PERIPHERAL_APBC_0
CLK_PERIPHERAL_APBC_1
CLK_PERIPHERAL_APBC_n
APBCMASK
APBBMASK
APBAMASK
CPUDIV
AHBMASK
CLK_CPU
GCLK
GCLK_MAIN
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
Clock
gate
CLK_MAIN
16.6.2.5 Clock Ready Flag
There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes
effective. During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register
(INTFLAG.CKRDY) will read as zero. If CKRDY in the INTENSET register is written to one, the Power
Manager interrupt can be triggered when the new clock setting is effective. CPUSEL must not be re-
written while CKRDY is zero, or the system may become unstable or hang.
16.6.2.6 Peripheral Clock Masking
It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing
the corresponding bit in the Clock Mask register (APBxMASK) to zero or one. Refer to the table below for
the default state of each of the peripheral clocks.
Table 16-1. Peripheral Clock Default State
Peripheral Clock Default State
CLK_PAC0_APB Enabled
CLK_PM_APB Enabled
CLK_SYSCTRL_APB Enabled
CLK_GCLK_APB Enabled
CLK_WDT_APB Enabled
CLK_RTC_APB Enabled
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 144