Datasheet

16.6.2.2 Enabling, Disabling and Resetting
The PM module is always enabled and can not be reset.
16.6.2.3 Selecting the Main Clock Source
Refer to GCLK – Generic Clock Controller for details on how to configure the main clock source.
Related Links
15. GCLK - Generic Clock Controller
16.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By
default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division
for the CPU clock by writing the CPU Prescaler Selection bits in the CPU Select register
(CPUSEL.CPUDIV), resulting in a CPU clock frequency determined by this equation:

CPU
=

main
2
CPUDIV
Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV).
To ensure correct operation, frequencies must be selected so that f
CPU
≥ f
APBx
. Also, frequencies must
never exceed the specified maximum frequency for each clock domain.
Note: The AHB clock is always equal to the CPU clock.
CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL
and APBxSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is
possible to keep one or more clocks unchanged. This way, it is possible to, for example, scale the CPU
speed according to the required performance, while keeping the APBx frequency constant.
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 143