Datasheet

16.5.8 Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
• Interrupt Flag register (INTFLAG).
• Reset Cause register (RCAUSE).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Write-protection does not apply for accesses through an external debugger. Refer to PAC – Peripheral
Access Controller for details.
Related Links
11.6 PAC - Peripheral Access Controller
16.5.9 Analog Connections
Not applicable.
16.6 Functional Description
16.6.1 Principle of Operation
16.6.1.1 Synchronous Clocks
The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common
root for the synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit
prescaler, and each of the derived clocks can run from any tapping off this prescaler or the undivided
main clock, as long as f
CPU
≥ f
APBx
. The synchronous clock source can be changed on the fly to respond
to varying load in the application. The clocks for each module in each synchronous clock domain can be
individually masked to avoid power consumption in inactive modules. Depending on the sleep mode,
some clock domains can be turned off (see Table 16-4).
16.6.1.2 Reset Controller
The Reset Controller collects the various reset sources and generates reset for the device. The device
contains a Power-on-Reset (POR) detector, which keeps the system reset until power is stable. This
eliminates the need for external reset circuitry to guarantee stable operation when powering up the
device.
16.6.1.3 Sleep Mode Controller
In Active mode, all clock domains are active, allowing software execution and peripheral operation. The
PM Sleep Mode Controller allows the user to choose between different sleep modes depending on
application requirements, to save power (see Table 16-4).
16.6.2 Basic Operation
16.6.2.1 Initialization
After a Power-on Reset (POR), the PM is enabled and the Reset Cause register indicates the POR
source (RCAUSE.POR). The default clock source of the GCLK_MAIN clock is started and calibrated
before the CPU starts running. The GCLK_MAIN clock is selected as the main clock without any division
on the prescaler. The device is in the Active mode.
By default, only the necessary clocks are enabled (see Table 16-1).
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 142