Datasheet

16.5.3 Clocks

The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Power Manager, and the default

state of CLK_PM_APB can be found in Peripheral Clock Default State table in the Peripheral Clock

Masking section. If this clock is disabled in the Power Manager, it can only be re-enabled by a reset.

A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN

is configured by default in the Generic Clock Controller, and can be reconfigured by the user if needed.

Refer to GCLK – Generic Clock Controller for details.

Related Links

16.6.2.6 Peripheral Clock Masking

15. GCLK - Generic Clock Controller

16.5.3.1 Main Clock

The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the

common 8-bit prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx

modules.

16.5.3.2 CPU Clock

The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing

instructions.

16.5.3.3 AHB Clock

The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB

clock is always synchronous to the CPU clock and has the same frequency, but may run even when the

CPU clock is turned off. A clock gate is inserted from the common AHB clock to any AHB clock of a

peripheral.

16.5.3.4 APBx Clocks

The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx

bus. The APBx clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will

run even when the CPU clock is turned off. A clock gater is inserted from the common APB clock to any

APBx clock of a module on APBx bus.

16.5.4 DMA

Not applicable.

16.5.5 Interrupts

The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the

Interrupt Controller to be configured first. Refer to Nested Vector Interrupt Controller for details.