Datasheet

16. PM – Power Manager
16.1 Overview
The Power Manager (PM) controls the reset, clock generation and sleep modes of the device.
Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller
provides synchronous system clocks to the CPU and the modules connected to the AHB and the APBx
bus. The synchronous system clocks are divided into a number of clock domains; one for the CPU and
AHB and one for each APBx. Any synchronous system clock can be changed at run-time during normal
operation. The clock domains can run at different speeds, enabling the user to save power by running
peripherals at a relatively low clock frequency, while maintaining high CPU performance. In addition, the
clock can be masked for individual modules, enabling the user to minimize power consumption.
Before entering the Stand-by Sleep mode the user must make sure that a significant amount of clocks
and peripherals are disabled, so that the voltage regulator is not overloaded. This is because during
Stand-by Sleep mode the internal voltage regulator will be in Low-Power mode.
Various sleep modes are provided in order to fit power consumption requirements. This enables the PM
to stop unused modules in order to save power. In active mode, the CPU is executing application code.
When the device enters a Sleep mode, program execution is stopped and some modules and clock
domains are automatically switched off by the PM according to the Sleep mode. The application code
decides which Sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset
sources can restore the device from a Sleep mode to Active mode.
The PM also contains a reset controller to collect all possible reset sources. It issues a device reset and
sets the device to its initial state, and allows the reset source to be identified by software.
16.2 Features
• Reset control
– Reset the microcontroller and set it to an initial state according to the reset source
– Multiple reset sources
• Power reset sources: POR, BOD12, BOD33
• User reset sources: External reset (RESET), Watchdog Timer reset, software reset
– Reset status register for reading the reset source from the application code
• Clock control
– Controls CPU, AHB and APB system clocks
• Multiple clock sources and division factor from GCLK
• Clock prescaler with 1x to 128x division
– Safe run-time clock switching from GCLK
– Module-level clock gating through maskable peripheral clocks
• Power management control
– Sleep modes: IDLE, STANDBY
– SleepWalking support on GCLK clocks
SAM D21 Family
PM – Power Manager
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 139