Datasheet

15.8.5 Generic Clock Generator Division
Name: GENDIV
Offset: 0x8
Reset: 0x00000000
Property: -
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
DIV[15:8]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
DIV[7:0]
Access
R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ID[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bits 23:8 – DIV[15:0] Division Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each
generator has can be seen in the next table. Writes to bits above the specified number will be ignored.
Generator Division Factor Bits
Generic clock generator 0 8 division factor bits - DIV[7:0]
Generic clock generator 1 16 division factor bits - DIV[15:0]
Generic clock generators 2 5 division factor bits - DIV[4:0]
Generic clock generators 3 - 8 8 division factor bits - DIV[7:0]
Bits 3:0 – ID[3:0] Generic Clock Generator Selection
These bits select the generic clock generator on which the division factor will be applied, as shown in the
table below.
Values Description
0x0 Generic clock generator 0
0x1 Generic clock generator 1
0x2 Generic clock generator 2
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 136