Datasheet

Bit 19 – OE Output Enable
This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a
source in the GENCLK.SRC bit group.
Value Description
0
The generic clock generator is not output.
1
The generic clock generator is output to the corresponding GCLK_IO, unless the
corresponding GCLK_IO is selected as a source in the GENCLK.SRC bit group.
Bit 18 – OOV Output Off Value
This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the
GENCLK.SRC bit group.
Value Description
0
The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit
is zero.
1
The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit
is zero.
Bit 17 – IDC Improve Duty Cycle
This bit is used to improve the duty cycle of the generic clock generator when odd division factors are
used.
Value Description
0
The generic clock generator duty cycle is not 50/50 for odd division factors.
1
The generic clock generator duty cycle is 50/50.
Bit 16 – GENEN Generic Clock Generator Enable
This bit is used to enable and disable the generic clock generator.
Value Description
0
The generic clock generator is disabled.
1
The generic clock generator is enabled.
Bits 12:8 – SRC[4:0] Source Select
These bits define the clock source to be used as the source for the generic clock generator, as shown in
the table below.
Value Name Description
0x00
XOSC XOSC oscillator output
0x01
GCLKIN Generator input pad
0x02
GCLKGEN1 Generic clock generator 1 output
0x03
OSCULP32K OSCULP32K oscillator output
0x04
OSC32K OSC32K oscillator output
0x05
XOSC32K XOSC32K oscillator output
0x06
OSC8M OSC8M oscillator output
0x07
DFLL48M DFLL48M output
0x08
FDPLL96M FDPLL96M output
0x09-0x
1F
Reserved Reserved for future use
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 133