Datasheet

15.8.4 Generic Clock Generator Control
Name: GENCTRL
Offset: 0x4
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RUNSTDBY DIVSEL OE OOV IDC GENEN
Access
R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
SRC[4:0]
Access
R/W R/W R/W R/W R/W
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
ID[3:0]
Access
R/W R/W R/W R/W
Reset 0 0 0 0
Bit 21 – RUNSTDBY Run in Standby
This bit is used to keep the generic clock generator running when it is configured to be output to its
dedicated GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator
will only be running if a peripheral requires the clock.
Value Description
0
The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero)
will be dependent on the setting in GENCTRL.OOV.
1
The generic clock generator is kept running and output to its dedicated GCLK_IO pin during
standby mode.
Bit 20 – DIVSEL Divide Selection
This bit is used to decide how the clock source used by the generic clock generator will be divided. If the
clock source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the
corresponding generic clock generator must be zero or one.
Value Description
0
The generic clock generator equals the clock source divided by GENDIV.DIV.
1
The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1).
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 132