Datasheet

...........continued
Module
Instance
Reset Value after a User Reset
CLKCTRL.GEN CLCTRL.CLKEN CLKCTRL.WRTLOCK
WDT 0x02 if WRTLOCK=0
No change if WRTLOCK=1
If WRTLOCK=0
0x01 if WDT Enable bit in NVM User
Row written to one
0x00 if WDT Enable bit in NVM User
Row written to zero
If WRTLOCK=1 no change
No change
Others 0x00 if WRTLOCK=0
No change if WRTLOCK=1
0x00 if WRTLOCK=0
No change if WRTLOCK=1
No change
Value Name Description
0x00
GCLK_DFLL48M_REF DFLL48M Reference
0x01
GCLK_DPLL FDPLL96M input clock source for reference
0x02
GCLK_DPLL_32K FDPLL96M 32 kHz clock for FDPLL96M internal lock
timer
0x03
GCLK_WDT WDT
0x04
GCLK_RTC RTC
0x05
GCLK_EIC EIC
0x06
GCLK_USB USB
0x07
GCLK_EVSYS_CHANNEL_0 EVSYS_CHANNEL_0
0x08
GCLK_EVSYS_CHANNEL_1 EVSYS_CHANNEL_1
0x09
GCLK_EVSYS_CHANNEL_2 EVSYS_CHANNEL_2
0x0A
GCLK_EVSYS_CHANNEL_3 EVSYS_CHANNEL_3
0x0B
GCLK_EVSYS_CHANNEL_4 EVSYS_CHANNEL_4
0x0C
GCLK_EVSYS_CHANNEL_5 EVSYS_CHANNEL_5
0x0D
GCLK_EVSYS_CHANNEL_6 EVSYS_CHANNEL_6
0x0E
GCLK_EVSYS_CHANNEL_7 EVSYS_CHANNEL_7
0x0F
GCLK_EVSYS_CHANNEL_8 EVSYS_CHANNEL_8
0x10
GCLK_EVSYS_CHANNEL_9 EVSYS_CHANNEL_9
0x11
GCLK_EVSYS_CHANNEL_10 EVSYS_CHANNEL_10
0x12
GCLK_EVSYS_CHANNEL_11 EVSYS_CHANNEL_11
0x13
GCLK_SERCOMx_SLOW SERCOMx_SLOW
0x14
GCLK_SERCOM0_CORE SERCOM0_CORE
0x15
GCLK_SERCOM1_CORE SERCOM1_CORE
0x16
GCLK_SERCOM2_CORE SERCOM2_CORE
0x17
GCLK_SERCOM3_CORE SERCOM3_CORE
0x18
GCLK_SERCOM4_CORE SERCOM4_CORE
0x19
GCLK_SERCOM5_CORE SERCOM5_CORE
0x1A
GCLK_TCC0, GCLK_TCC1 TCC0,TCC1
0x1B
GCLK_TCC2, GCLK_TC3 TCC2,TC3
0x1C
GCLK_TC4, GCLK_TC5 TC4,TC5
0x1D
GCLK_TC6, GCLK_TC7 TC6,TC7
0x1E
GCLK_ADC ADC
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 130