Datasheet

15.8.2 Status
Name: STATUS
Offset: 0x1
Reset: 0x00
Property: -
Bit 7 6 5 4 3 2 1 0
SYNCBUSY
Access
R
Reset 0
Bit 7 – SYNCBUSY Synchronization Busy Status
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 127