Datasheet

15.8.1 Control
Name: CTRL
Offset: 0x0
Reset: 0x00
Property: Write-Protected, Write-Synchronized
Bit 7 6 5 4 3 2 1 0
SWRST
Access
R/W
Reset 0
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for
generic clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one.
Refer to GENCTRL.ID for details on GENCTRL reset.
Refer to GENDIV.ID for details on GENDIV reset.
Refer to CLKCTRL.ID for details on CLKCTRL reset.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete.
CTRL.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value Description
0
There is no reset operation ongoing.
1
There is a reset operation ongoing.
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 126