Datasheet

15.7 Register Summary
Offset Name Bit Pos.
0x00 CTRL 7:0 SWRST
0x01 STATUS 7:0 SYNCBUSY
0x02 CLKCTRL
7:0 ID[5:0]
15:8 WRTLOCK CLKEN GEN[3:0]
0x04 GENCTRL
7:0 ID[3:0]
15:8 SRC[4:0]
23:16 RUNSTDBY DIVSEL OE OOV IDC GENEN
31:24
0x08 GENDIV
7:0 ID[3:0]
15:8 DIV[7:0]
23:16 DIV[15:8]
31:24
15.8 Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Refer to 15.5.8 Register Access Protection for details.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
Refer to 15.6.6 Synchronization for details.
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 125