Datasheet

15.6.5 Sleep Mode Operation

15.6.5.1 Sleep Walking

The GCLK module supports the Sleep Walking feature. If the system is in a sleep mode where the

Generic Clocks are stopped, a peripheral that needs its clock in order to execute a process must request

it from the Generic Clock Controller.

The Generic Clock Controller receives this request, determines which Generic Clock Generator is

involved and which clock source needs to be awakened. It then wakes up the respective clock source,

enables the Generator and generic clock stages successively, and delivers the clock to the peripheral.

15.6.5.2 Run in Standby Mode

In standby mode, the GCLK can continuously output the generator output to GCLK_IO.

When set, the GCLK can continuously output the generator output to GCLK_IO.

Refer to 15.6.2.9 Generic Clock Output on I/O Pins for details.

15.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers

need to be synchronized when written or read.

When executing an operation that requires synchronization, the Synchronization Busy bit in the Status

If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be

stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending

as long as the bus is stalled.

The following registers are synchronized when written:

• Generic Clock Generator Control register (GENCTRL)

• Generic Clock Generator Division register (GENDIV)

• Control register (CTRL)

Required write-synchronization is denoted by the "Write-Synchronized" property in the register

description.