Datasheet

Refer to PM-Power Manager for details on the synchronous clock generation.
Figure 15-3. Generic Clock Generator
Clock Sources
0
1
GENCTRL.DIVSEL
GENCTRL.GENEN
GENDIV.DIV
GENCTRL.SRC
GCLKGENSRC
GCLK_IO[x]
GCLKGENSRC
DIVIDER
Clock
Gate
GCLKGEN[x]
Related Links
16. PM – Power Manager
15.6.2.4 Enabling a Generic Clock Generator
A Generator is enabled by setting the Generic Clock Generator Enable bit in the Generic Clock Generator
Control register (GENCTRL.GENEN=1).
15.6.2.5 Disabling a Generic Clock Generator
A Generator is disabled by clearing GENCTRL.GENEN. When GENCTRL.GENEN=0, the GCLKGEN
clock is disabled and clock gated.
15.6.2.6 Selecting a Clock Source for the Generic Clock Generator
Each Generator can individually select a clock source by setting the Source Select bit group in GENCTRL
(GENCTRL.SRC).
Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If
clock source B is not ready, the Generator will continue running with clock source A. As soon as clock
source B is ready, however, the generic clock generator will switch to it. During the switching operation,
the Generator holds clock requests to clock sources A and B and then releases the clock source A
request when the switch is done.
The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and
DFLL). Only GCLKGEN[1] can be used as a common source for all other generators except Generator 1.
Note: Before switching the Generic Clock Generator 0 (GCLKGEN0) from a clock source A to another
clock source B, enable the "ONDEMAND" feature of the clock source A to ensure a proper transition from
clock source A to clock source B.
15.6.2.7 Changing Clock Frequency
The selected source (GENCLKSRC) for a Generator can be divided by writing a division value in the
Division Factor bit group in the Generic Clock Generator Division register (GENDIV.DIV). How the actual
division factor is calculated is depending on the Divide Selection bit in GENCTRL (GENCTRL.DIVSEL), it
can be interpreted in two ways by the integer divider.
Note: The number of DIV bits for each Generator is device dependent.
15.6.2.8 Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing the Improve
Duty Cycle bit in GENCTRL (GENCTRL.IDC=1) will result in a 50/50 duty cycle.
SAM D21 Family
GCLK - Generic Clock Controller
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Datasheet Complete
DS40001882D-page 121