Datasheet

15.6.2 Basic Operation
15.6.2.1 Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock
must be configured as outlined by the following steps:
1. The Generic Clock Generator division factor must be set by performing a single 32-bit write to the
Generic Clock Generator Division register (GENDIV):
– The Generic Clock Generator that will be selected as the source of the generic clock by
setting the ID bit group (GENDIV.ID).
– The division factor must be selected by the DIV bit group (GENDIV.DIV)
Note: Refer to Generic Clock Generator Division register (GENDIV) for details.
2. The generic clock generator must be enabled by performing a single 32-bit write to the Generic
Clock Generator Control register (GENCTRL):
– The Generic Clock Generator will be selected as the source of the generic clock by the ID bit
group (GENCTRL.ID)
– The Generic Clock generator must be enabled (GENCTRL.GENEN=1)
Note: Refer to Generic Clock Generator Control register (GENCTRL) for details.
3. The generic clock must be configured by performing a single 16-bit write to the Generic Clock
Control register (CLKCTRL):
– The Generic Clock that will be configured via the ID bit group (CLKCTRL.ID)
– The Generic Clock Generator used as the source of the generic clock by writing the GEN bit
group (CLKCTRL.GEN)
Note: Refer to Generic Clock Control register (CLKCTRL) for details.
Related Links
15.8.5 GENDIV
15.8.4 GENCTRL
15.8.3 CLKCTRL
15.6.2.2 Enabling, Disabling and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by setting the Software Reset bit in the Control register (CTRL.SWRST) to 1. All
registers in the GCLK will be reset to their initial state, except for Generic Clocks Multiplexer and
associated Generators that have their Write Lock bit set to 1 (CLKCTRL.WRTLOCK). For further details,
refer to 15.6.3.4 Configuration Lock.
15.6.2.3 Generic Clock Generator
Each Generator (GCLK_GEN) can be set to run from one of eight different clock sources except
GCLKGEN[1], which can be set to run from one of seven sources. GCLKGEN[1] is the only Generator
that can be selected as source to other Generators but can not act as source to itself.
Each generator GCLKGEN[x] can be connected to one specific pin GCLK_IO[x]. The GCLK_IO[x] can be
set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by
GCLKGEN[x].
The selected source can be divided. Each Generator can be enabled or disabled independently.
Each GCLKGEN clock signal can then be used as clock source for Generic Clock Multiplexers. Each
Generator output is allocated to one or several Peripherals.
GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager.
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 120