Datasheet

Introducing Frame Synch Clock.

29.4 Signal Description: Added separate tables for Master-, Slave- and Controller mode.

Updated description in 29.5.7 Debug Operation and 29.5.8 Register Access Protection.

Updated description in 29.6.1 Principle of Operation.

Updated description in sub sections of 29.6.2 Basic Operation.

Updated formula in 29.6.2.1.3 MCKn Clock Frequency.

Updated formulas in 29.6.2.1.5 Relation Between MCKn, SCKn, and Sampling Frequency fs.

Updated description in 29.6.6 PDM Reception.

Section on MONO removed and information included in 29.6.2 Basic Operation.

Updated property of Control A (CTRLA) register: Added Write-Synchronized

31. TCC – Timer/Counter for Control Applications

Updated description in 31.6.1 Principle of Operation.

Updated description in sub sections of 31.6.2 Basic Operation.

Updated description in sub sections of 31.6.3 Additional Features.

Updated description in 31.6.6 Synchronization.

Lock Update (LUPD) bit description updated in Control B Clear (CTRLBCLR) register.

Compare Channel Buffer x Busy (CCBx) bit description updated in Synchronization Busy (SYNCBUSY)

Event Control (EVCTRL) register property updated: Removed Enable-Protected.

Interrupt Enable Clear (INTENCLR), Interrupt Enable Set (INTENSET) and Interrupt Flag Status and

Clear (INTFLAG) registers: Updated bit description of FAULT0, FAULT1, FAULTA and FAULTB.

STATUS register bit descriptions updated.

Wave Control (WAVE) register property updated: Removed Read-Synchronized.

Pattern Buffer (PATTB) register: Updated property and bit description.

Waveform Control Buffer (WAVEB) register: Updated property and bit descriptions.

32. USB – Universal Serial Bus

Removed figures: Setup Transaction Overview, OUT Single Bank Transaction Overview, IN Single Bank

Transaction Overview and USB Host Communication Flow.

Updated description and graphics in sub sections of 32.6.2 USB Device Operations.

Updated description in sub sections of 32.6.3 Host Operations.

Pad Calibration (PADCAL) register: Access updated.

Upgraded bit descriptions.

32.8.7.1 Pipe Descriptor Structure: Updated register reset values.

33. ADC – Analog-to-Digital Converter

SAM D21 Family

Data Sheet Revision History

Datasheet Complete

DS40001882D-page 1194