Datasheet

Register Summary and Register Description:
EVCTRL register: Added bits EXTINTO17 and EXTINTO16 in bit position 17 and 16 respectively.
INTENCLR, INTENSET, INTENFLAG registers: Added bits EXTINT17 and EXTINT16 in bit position 17
and 16 respectively.
WAKEUP register: Added bits WAKEUPEN17 and WAKEUPEN16 in bit position 17 and 16 respectively.
CONFIG2 register added, CONFIG0 and CONFIG1 registers updated: Added bits FILTEN0...31 and
SENSE0...31.
22. NVMCTRL – Nonvolatile Memory Controller
CTRLB register: Removed table from NVM Read Wait States description (RWS[3:0])
23. PORT - I/O Pin Controller
Instances of the term “pad” replaced with “pin”.
Instances of the term “bundle” replaced with “group” and “interface”.
23.6.2 Basic Operation description updated.
Peripheral Multiplexing n (PMUX0) register: Offset formula updated.
24. EVSYS – Event System
Updated information in 24.2 Features.
24.5.2 Power Management updated: Description of on how event generators can generate an event
when the system clock is stopped moved to 24.6.4 Sleep Mode Operation.
24.5.3 Clocks updated: Renamed EVSYS channel dedicated generic clock from GCLK_EVSYS_x to
GCLK_EVSYS_CHANNELx.
Updated description in 24.6.1 Principle of Operation.
Updated description in sub sections of 24.6.2 Basic Operation.
Updated description in 24.6.3.1 The Overrun Channel n Interrupt.
Channel x Overrun bit description in 24.8.7 INTFLAG updated.
26. SERCOM USART
Updated description in 26.6.3.4 Break Character Detection and Auto-Baud.
Updated description in 26.6.3.7 Start-of-Frame Detection.
29. I2S - Inter-IC Sound Controller
SAM D21 Family
Data Sheet Revision History
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1193