Datasheet

15.5.2 Power Management
The GCLK can operate in sleep modes, if required. Refer to the sleep mode description in the Power
Manager (PM) section.
Related Links
16. PM – Power Manager
15.5.3 Clocks
The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the
default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section of PM – Power
Manager.
Related Links
16. PM – Power Manager
15.5.4 DMA
Not applicable.
15.5.5 Interrupts
Not applicable.
15.5.6 Events
Not applicable.
15.5.7 Debug Operation
Not applicable.
15.5.8 Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller
(PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
Write-protection does not apply for accesses through an external debugger.
Related Links
11.6 PAC - Peripheral Access Controller
15.5.9 Analog Connections
Not applicable.
15.6 Functional Description
15.6.1 Principle of Operation
The GCLK module is comprised of eight Generic Clock Generators (Generators) sourcing m Generic
Clock Multiplexers.
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the
Generator. A generator output is used as input to one or more the Generic Clock Multiplexers to provide a
peripheral (GCLK_PERIPHERAL). A generic clock can act as the clock to one or several of peripherals.
SAM D21 Family
GCLK - Generic Clock Controller
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 119