Datasheet

Added pinout figures for 5.1.2 UFBGA64 and 5.2.2 WLCSP45.
9. Product Mapping:
Updated Product Mapping figure with Internal RWW section block for Device Variant B.
10. Memories:
10.2 Physical Memory Map: Added start address for Internal Read While Write (RWW)
section for Device Variant B.
11. Processor And Architecture:
11.1.1 Cortex M0+ Configuration: Removed green connection dots between DMAC Data
and AHB-APB Bridge A and Bridge B.
22. NVMCTRL – Nonvolatile Memory Controller:
Introducing Read While Write (RWW) feature for Device Variant B.
Updated and New sections:
22.1 Overview
22.2 Features
22.3 Block Diagram
22.6.4.1 NVM Read
22.6.4.2 RWWEE Read
22.6.4.3 NVM Write
22.6.4.5 Erase Row
22.6.2 Memory Organization: Figure 22-2 updated.
Register Summary and 22.8 Register Description: 22.8.3 PARAM: Added
RWWEEP[12:0] bits for Device Variant B.
23. PORT - I/O Pin Controller:
23.6.3 I/O Pin Configuration: Removed reference to “open-drain”.
Access for DRVSTR bit in Pin Configuration n register (PINCFGn.DRVCTR) updated from
W to R/W.
17. SYSCTRL – System Controller:
Removed references to XOSC32K and OSC32 1kHz clock output option:
- XOSC32K: 17.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
- OSC32K: 17.6.4 32kHz Internal Oscillator (OSC32K) Operation
1kHz Output Enable (EN1K) bit set as reserved bit:
- Bit 4 in 17.8.6 XOSC32K
- Bit 3 in 17.8.7 OSC32K
37. Electrical Characteristics:
SAM D21 Family
Data Sheet Revision History
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1189