Datasheet

Figure 15-2. Generic Clock Controller Block Diagram
(1)
Generic Clock Generator 0
GCLK_IO[0]
(I/O input)
Clock
Divider &
Masker
Clock Sources
GCLKGEN[0]
GCLK_IO[1]
(I/O input)
GCLKGEN[1]
GCLK_IO[n]
(I/O input)
GCLKGEN[n]
Clock
Gate
Generic Clock Multiplexer 0
GCLK_PERIPHERAL[0]
Clock
Gate
Generic Clock Multiplexer 1
Clock
Gate
Generic Clock Multiplexer m
GCLKGEN[n:0]
GCLK_MAIN
GCLK_IO[1]
(I/O output)
GCLK_IO[0]
(I/O output)
GCLK_IO[n]
(I/O output)
Generic Clock Generator 1
Clock
Divider &
Masker
Generic Clock Generator n
Clock
Divider &
Masker
GCLK_PERIPHERAL[1]
GCLK_PERIPHERAL[m]
Note: 1. If GENCTRL.SRC=0x01(GCLKIN), the GCLK_IO is set as an input.
15.4 Signal Description
Table 15-1. Signal Description
Signal Name Type Description
GCLK_IO[7:0] Digital I/O Clock source for Generators when input
Generic Clock signal when output
Refer to PORT Function Multiplexing table in I/O Multiplexing and Considerations for details on the pin
mapping for this peripheral.
Note: One signal can be mapped on several pins.
Related Links
7. I/O Multiplexing and Considerations
15.5 Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
15.5.1 I/O Lines
Using the GCLK I/O lines requires the I/O pins to be configured.
Related Links
23. PORT - I/O Pin Controller
SAM D21 Family
GCLK - Generic Clock Controller
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Datasheet Complete
DS40001882D-page 118