Datasheet

Figure 42-12. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
VTG
GND
NC
NC
SWDIO
SWDCLK
NC
NC
RESET
10-pin JTAGICE3 Compatible
Serial Wire Debug Header
GND
SWDIO
SWCLK
RESET
V
DD
1
NC
Table 42-11. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
Header Signal Name Description
SWDCLK Serial wire clock pin
SWDIO Serial wire bidirectional data pin
RESET Target device reset pin, active low
VTG Target voltage sense, should be connected to the device V
DD
GND Ground
42.7.3 20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the
signals should be connected as shown in the next figure with details described in the table.
SAM D21 Family
Schematic Checklist
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1172