Datasheet

frequency as well as the divider used in the Generic Clock Generator. The total startup time Tstart from a
clock request until the clock is available for the peripheral is between:
T
start_max
= Clock source startup time + 2 × clock source periods + 2 × divided clock source periods
T
start_min
= Clock source startup time + 1 × clock source period + 1 × divided clock source period
The time between the last active clock request stopped and the clock is shut down, T
stop
, is between:
T
stop_min
= 1 × divided clock source period + 1 × clock source period
T
stop_max
= 2 × divided clock source periods + 2 × clock source periods
The On-Demand function can be disabled individually for each clock source by clearing the ONDEMAND
bit located in each clock source controller. Consequently, the clock will always run whatever the clock
request status is. This has the effect of removing the clock source startup time at the cost of power
consumption.
The clock request mechanism can be configured to work in standby mode by setting the RUNSDTBY bits
of the modules, see Figure 14-4.
14.7 Power Consumption vs. Speed
When targeting for either a low-power or a fast acting system, some considerations have to be taken into
account due to the nature of the asynchronous clocking of the peripherals:
If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower.
At the same time the synchronization to the synchronous (CPU) clock domain is dependent on the
peripheral clock speed, and will take longer with a slower peripheral clock. This will cause worse
response times and longer synchronization delays.
14.8 Clocks after Reset
On any reset the synchronous clocks start to their initial state:
• OSC8M is enabled and divided by 8
• Generic Generator 0 uses OSC8M as source and generates GCLK_MAIN
• CPU and BUS clocks are undivided
On a Power Reset, the GCLK module starts to its initial state:
• All Generic Clock Generators are disabled except
– Generator 0 is using OSC8M as source without division and generates GCLK_MAIN
– Generator 2 uses OSCULP32K as source without division
• All Generic Clocks are disabled except:
– WDT Generic Clock uses the Generator 2 as source
On a User Reset the GCLK module starts to its initial state, except for:
• Generic Clocks that are write-locked , i.e., the according WRTLOCK is set to 1 prior to Reset or
WDT Generic Clock if the WDT Always-On at power on bit set in the NVM User Row
• Generic Clock is dedicated to the RTC if the RTC Generic Clock is enabled
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are
reset only by a power reset.
SAM D21 Family
Clock System
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 116