Datasheet

f
REF
Reference
frequency
- 0.732 32.768 33 kHz
Jitter Cycle to Cycle jitter f
REF
= XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
- - 0.42 ns
I
DFLL
Power
consumption on
V
DDIN
f
REF
= XTAL, 32 .768kHz, 100ppm - 403 457 µA
t
LOCK
Lock time f
REF
= XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
DFLLVAL.COARSE = DFLL48M COARSE
CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
- 350 1500 µs
Table 40-52. DFLL48M Characteristics - Close Loop Mode (Device Variant B and D)
Symbol Parameter Conditions Min. Typ. Max. Units
f
OUT
Average Output
frequency
f
REF
= XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
47.76 48 48.24 MHz
f
REF
Reference
frequency
- 0.732 32.768 33 kHz
Jitter Cycle to Cycle jitter f
REF
= XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
- - 0.42 ns
I
DFLL
Power
consumption on
V
DDIN
f
REF
= XTAL, 32 .768kHz, 100ppm - 403 457 µA
SAM D21 Family
AEC-Q100 125°C Specifications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1130