Datasheet

14.3.1.6 Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and
set STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The
Synchronisation Ready interrupt (if available) cannot be used for Enable write-synchronization.
When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the
following will cause the peripheral bus to stall until the enable synchronization is complete:
• Writing a peripheral core register
• Writing an APB register
• Reading a read-synchronized peripheral core register
APB registers can be read while the enable write-synchronization is ongoing without causing the
peripheral bus to stall.
14.3.1.7 Software Reset Write-Synchronization
Writing a '1' to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and
set STATUS.SYNCBUSY. When writing a '1' to the CTRL.SWRST bit it will immediately read as '1'.
CTRL.SWRST and STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been
reset. Writing a zero to the CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if
available) cannot be used for Software Reset write-synchronization.
When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are '1'), attempt to do
any of the following will cause the peripheral bus to stall until the Software Reset synchronization and the
reset is complete:
• Writing a peripheral core register
• Writing an APB register
• Reading a read-synchronized register
APB registers can be read while the software reset is being write-synchronized without causing the
peripheral bus to stall.
14.3.1.8 Synchronization Delay
The synchronization will delay write and read accesses by a certain amount. This delay D is within the
range of:
5 × 
GCLK
+ 2 × 
APB
<  < 6 × 
GCLK
+ 3 × 
APB
Where 
GCLK
is the period of the generic clock and 
APB
is the period of the peripheral bus clock. A
normal peripheral bus register access duration is 2 × 
APB
.
14.3.2 Distributed Synchronizer Register Synchronization
14.3.2.1 Overview
All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running
from a corresponding clock in the Main Clock domain, and one peripheral core running from the
peripheral Generic Clock (GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in
hardware, so the synchronization process takes place even if the peripheral generic clock is running from
the same clock source and on the same frequency as the bus interface.
All registers in the bus interface are accessible without synchronization. All registers in the peripheral
core are synchronized when written. Some registers in the peripheral core are synchronized when read.
Registers that need synchronization has this denoted in each individual register description.
SAM D21 Family
Clock System
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 113