Datasheet

Note:
1. These values are based on characterization. These values are not covered by test limits in
production.
2. These values are based on simulation. These values are not covered by test limits in production or
characterization.
3. In this condition and for a sample rate of 350ksps, 1 Conversion at gain 1x takes 6 clock cycles of
the ADC clock.
4. All single-shot measurements are performed with V
DDANA
> 3.0V (cf. ADC errata).
Table 40-26. Differential Mode : FCLK_ADC = 2.1MHz (Device Variant A)
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation - 9.9 10.1 bits
TUE Total Unadjusted Error 1x Gain 2.9 4.6 12.4 LSB
INL Integral Non Linearity 1x Gain 1.4 2.2 6.5 LSB
DNL Differential Non Linearity 1x Gain +/-0.3 +/-0.5 +/-0.95 LSB
Gain Error Ext. Ref 1x -24 -2.5 24 mV
V
REF
=V
DDANA
/1.48 -25 -1.5 25 mV
Bandgap -13 -5 +13 mV
Gain Accuracy
(5)
Ext. Ref. 0.5x +/-0.1 +/-0.2 +/-0.45 %
Ext. Ref. 2x to 16x +/-0.1 +/-0.2 +/-2 %
Offset Error Ext. Ref. 1x -10 -2 10 mV
V
REF
=V
DDANA
/1.48 -10 0.5 15 mV
Bandgap -10 3 15 mV
SFDR Spurious Free Dynamic Range 1x Gain
F
IN
= 40kHz
A
IN
= 95%FSR
64.2 70 78.9 dB
SINAD Signal-to-Noise and Distortion 60.4 61.1 62.7 dB
SNR Signal-to-Noise Ratio 63.4 64.4 66 dB
THD Total Harmonic Distortion -65.0 -64.0 -62.6 dB
Noise RMS T=25°C 0.6 1 2.5 mV
Table 40-27. Differential Mode : FCLK_ADC = 2.1MHz (Device Variant B and D)
Symbol Parameter Conditions Min. Typ. Max. Units
ENOB Effective Number Of Bits With gain compensation - 10.5 10.8 bits
TUE Total Unadjusted Error 1x Gain 1.5 2.9 14 LSB
INL Integral Non Linearity 1x Gain 0.9 1.3 4 LSB
DNL Differential Non Linearity 1x Gain +/-0.3 +/-0.5 +/-0.95 LSB
SAM D21 Family
AEC-Q100 125°C Specifications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1117