Datasheet

Each individual register description will have the properties "Read-Synchronized" and/or "Write-
Synchronized" if a register is synchronized.
As shown in the figure below, the common synchronizer is used for all registers in one peripheral.
Therefore, status register (STATUS) of each peripheral can be synchronized at a time.
Figure 14-3. Synchronization
Non Synced reg
INTFLAG
STATUS
READREQ
Write-Synced reg
Write-Synced reg
R/W-Synced reg
Synchronizer
Sync
SYNCBUSY
Synchronous Domain
(CLK_APB)
Asynchronous Domain
(generic clock)
Peripheral bus
14.3.1.2 Write-Synchronization
Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The
Synchronization Busy bit in the Status register (STATUS.SYNCBUSY) will be set when the write-
synchronization starts and cleared when the write-synchronization is complete. Refer to 14.3.1.8
Synchronization Delay for details on the synchronization delay.
When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will
cause the peripheral bus to stall until the synchronization is complete:
SAM D21 Family
Clock System
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Datasheet Complete
DS40001882D-page 111