Datasheet

– CPU, AHB clocks undivided
– APBA clock divided by 4
– APBB and APBC bridges off
• The following AHB module clocks are running: NVMCTRL, APBA bridge
– All other AHB clocks stopped
• The following peripheral clocks running: PM, SYSCTRL, RTC
– All other peripheral clocks stopped
• I/Os are inactive with internal pull-up
• CPU is running on Flash with 1 wait states
• NVMCTRL cache enabled
• BOD33 disabled
Table 40-10. Current Consumption (Device Variant A)
Mode Conditions TA VCC Typ. Max. Units
ACTIVE CPU running a While 1
algorithm
25°C 3.3V 3.4 3.9 mA
125°C 3.3V 3.8 6.1
CPU running a While 1
algorithm, with
GCLKIN as reference
25°C 3.3V 60*Freq+136 81*Freq+126 µA
(with freq. in
MHz)
125°C 3.3V 62*Freq+498 70*Freq
+1780
CPU running a Fibonacci
algorithm
25°C 3.3V 4.6 5.0 mA
125°C 3.3V 5.0 7.3
CPU running a Fibonacci
algorithm, with
GCLKIN as reference
25°C 3.3V 92*Freq+113 99*Freq+141 µA
(with freq. in
MHz)
125°C 3.3V 92*Freq+503 91*Freq
+1794
CPU running a CoreMark
algorithm
25°C 3.3V 6.3 6.8 mA
125°C 3.3V 6.7 8.6
CPU running a CoreMark
algorithm, with
GCLKIN as reference
25°C 3.3V 118*Freq
+116
131*Freq
+141
µA
(with freq. in
MHz)
125°C 3.3V 121*Freq
+506
122*Freq
+1792
IDLE0 Default operating conditions 25°C 3.3V 2.0 2.2 mA
125°C 3.3V 2.4 4.0
IDLE1 Default operating conditions 25°C 3.3V 1.5 1.6
125°C 3.3V 1.8 3.3
IDLE2 Default operating conditions 25°C 3.3V 1.2 1.3
125°C 3.3V 1.5 3.0
SAM D21 Family
AEC-Q100 125°C Specifications
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1105