Datasheet

Table 40-8. Maximum GCLK Generator Output Frequencies (Device Variant B, D)
Symbol Description Conditions Max Units
f
GCLKGEN0
/
f
GCLK_MAIN
GCLK Generator
Output Frequency
Undivided 96 MHz
f
GCLKGEN1
Divided 48 MHz
f
GCLKGEN2
f
GCLKGEN3
f
GCLKGEN4
f
GCLKGEN5
Table 40-9. Maximum Peripheral Clock Frequencies (Device Variant B, D)
Symbol Description Max. Units
f
CPU
CPU clock frequency 48 MHz
f
AHB
AHB clock frequency 48 MHz
f
APBA
APBA clock frequency 48 MHz
f
APBB
APBB clock frequency 48 MHz
f
APBC
APBC clock frequency 48 MHz
f
GCLK_DFLL48M_REF
DFLL48M Reference clock frequency 33 KHz
f
GCLK_DPLL
FDPLL96M Reference clock frequency 2 MHz
f
GCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency 32 KHz
f
GCLK_WDT
WDT input clock frequency 48 MHz
f
GCLK_RTC
RTC input clock frequency 48 MHz
f
GCLK_EIC
EIC input clock frequency 48 MHz
f
GCLK_USB
USB input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency 48 MHz
f
GCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency 48 MHz
SAM D21 Family
AEC-Q100 125°C Specifications
© 2018 Microchip Technology Inc.
Datasheet Complete
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