Datasheet

Table 40-5. Supply Rates
Symbol Conditions
Fall Rate Rise Rate
Units
Max Max
V
DDIO
DC supply peripheral I/Os, internal regulator and analog supply
voltage
0.05 0.1 V/μsV
DDIN
V
DDANA
Note: To secure power up and power down sequence, enabling BOD33 is recommended.
Related Links
Power Supply and Start-Up Considerations
40.6 Maximum Clock Frequencies
Table 40-6. Maximum GCLK Generator Output Frequencies (Device Variant A)
Symbol Description Conditions Max Units
f
GCLKGEN0
/ f
GCLK_MAIN
GCLK Generator Output Frequency Undivided 64 MHz
f
GCLKGEN1
Divided 32 MHz
f
GCLKGEN2
f
GCLKGEN3
f
GCLKGEN4
f
GCLKGEN5
Table 40-7. Maximum Peripheral Clock Frequencies (Device Variant A)
Symbol Description Max. Units
f
CPU
CPU clock frequency 32 MHz
f
AHB
AHB clock frequency 32 MHz
f
APBA
APBA clock frequency 32 MHz
f
APBB
APBB clock frequency 32 MHz
f
APBC
APBC clock frequency 32 MHz
f
GCLK_DFLL48M_REF
DFLL48M Reference clock frequency 33 kHz
f
GCLK_DPLL
FDPLL96M Reference clock frequency 2 MHz
f
GCLK_DPLL_32K
FDPLL96M 32k Reference clock frequency 32 kHz
f
GCLK_WDT
WDT input clock frequency 48 MHz
f
GCLK_RTC
RTC input clock frequency 48 MHz
f
GCLK_EIC
EIC input clock frequency 48 MHz
SAM D21 Family
AEC-Q100 125°C Specifications
© 2018 Microchip Technology Inc.
Datasheet Complete
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