Datasheet

SERCOM0. The SERCOM0 interface, clocked by CLK_SERCOM0_APB, has been unmasked in the
APBC Mask register in the PM.
Figure 14-2. Example of SERCOM clock
SYSCTRL
DFLL48M
Generic Clock
Generator 1
Generic Clock
Multiplexer 20
SERCOM 0
Synchronous Clock
Controller
PM
CLK_SERCOM0_APB
GCLK_SERCOM0_CORE
GCLK
14.2 Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be in different clock domains, i.e. they are clocked from different
clock sources and/or with different clock speeds, some peripheral accesses by the CPU need to be
synchronized. In this case the peripheral includes a SYNCBUSY status register that can be used to check
if a sync operation is in progress.
For a general description, see 14.3 Register Synchronization. Some peripherals have specific properties
described in their individual sub-chapter “Synchronization”.
In the datasheet, references to Synchronous Clocks are referring to the CPU and bus clocks, while
asynchronous clocks are generated by the Generic Clock Controller (GCLK).
14.3 Register Synchronization
There are two different register synchronization schemes implemented on this device: common
synchronizer register synchronization and distributed synchronizer register synchronization.
The modules using a common synchronizer register synchronization are: GCLK, WDT, RTC, EIC, TC,
ADC, AC and DAC.
The modules adopting a distributed synchronizer register synchronization are: SERCOM USART,
SERCOM SPI, SERCOM I2C, I2S, TCC, USB.
14.3.1 Common Synchronizer Register Synchronization
14.3.1.1 Overview
All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running
from a corresponding clock in the Main Clock domain, and one peripheral core running from the
peripheral Generic Clock (GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in
hardware, so the synchronization process takes place even if the peripheral generic clock is running from
the same clock source and on the same frequency as the bus interface.
All registers in the bus interface are accessible without synchronization. All registers in the peripheral
core are synchronized when written. Some registers in the peripheral core are synchronized when read.
SAM D21 Family
Clock System
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 110