Datasheet

14. Clock System
This chapter summarizes the clock distribution and terminology in the SAM D21 device. It will not explain
every detail of its configuration. For in-depth documentation, see the respective peripherals descriptions
and the Generic Clock documentation.
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15. GCLK - Generic Clock Controller
14.1 Clock Distribution
Figure 14-1. Clock distribution
GCLK Generator 0
SYSCTRL
GCLK
GCLK Generator 1
GCLK Generator x
GCLK Multiplexer 0
(DFLL48M Reference)
GCLK Multiplexer 1
GCLK Multiplexer y
Peripheral z
Peripheral 0
Synchronous Clock
Controller
PM
AHB/APB System Clocks
GCLK_MAIN
OSC8M
OSC32K
OSCULP32K
XOSC32K
DFLL48M
XOSC
Generic
Clocks
FDPLL96M
The clock system on the SAM D21 consists of:
• Clock sources, controlled by SYSCTRL
– A clock source provides a time base that is used by other components, such as Generic
Clock Generators. Example clock sources are the internal 8MHz oscillator (OSC8M), External
crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M).
• Generic Clock Controller (GCLK) which controls the clock distribution system, made up of:
• Generic Clock Generators: These are programmable prescalers that can use any of the
system clock sources as a time base. The Generic Clock Generator 0 generates the clock
signal GCLK_MAIN, which is used by the Power Manager, which in turn generates
synchronous clocks.
• Generic Clocks: These are clock signals generated by Generic Clock Generators and output
by the Generic Clock Multiplexer, and serve as clocks for the peripherals of the system.
Multiple instances of a peripheral will typically have a separate Generic Clock for each
instance. Generic Clock 0 serves as the clock source for the DFLL48M clock input (when
multiplying another clock source).
• Power Manager (PM)
• The PM generates and controls the synchronous clocks on the system. This includes the
CPU, bus clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the
peripherals. It contains clock masks that can turn on/off the user interface of a peripheral as
well as prescalers for the CPU and bus clocks.
The next figure shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The
DFLL48M is enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source and feeds
into Peripheral Channel 20. The Generic Clock 20, also called GCLK_SERCOM0_CORE, is connected to
SAM D21 Family
Clock System
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 109