Datasheet

...........continued
Name Description Mode VDD=1.8V VDD=3.3V Units
Min. Typ. Max Min. Typ. Max.
t
PDM2LS
Data input setup
time
Master mode PDM2 Left 34.7 24.5 ns
t
PDM2LH
Data input hold time Master mode PDM2 Left -8.2 -8.2 ns
t
PDM2RS
Data input setup
time
Master mode PDM2
Right
30.5 20.9 ns
t
PDM2RH
Data input hold time Master mode PDM2
Right
-6.7 -6.7 ns
Table 37-72. I2S Timing Characteristics and Requirements (Device Variant B, C and D)
Name Description Mode VDD=1.8V VDD=3.3V Units
Min. Typ. Max. Min. Typ. Max.
t
M_MCKOR
I2S MCK rise time(3) Master mode /
Capacitive load CL =
15 pF
9.2 4.7 ns
t
M_MCKOF
I2S MCK fall time(3) Master mode /
Capacitive load CL =
15 pF
11.6 5.4 ns
d
M_MCKO
I2S MCK duty cycle Master mode 47.1 50 47.3 50 %
d
M_MCKI
I2S MCK duty cycle Master mode, pin is
input (1b)
50 50 %
t
M_SCKOR
I2S SCK rise time(3) Master mode /
Capacitive load CL =
15 pF
9 4.6 ns
t
M_SCKOF
I2S SCK fall time(3) Master mode /
Capacitive load CL =
15 pF
9.7 4.6 ns
d
M_SCKO
I2S SCK duty cycle Master mode 47 50 47.2 50 %
f
M_SCKO
, 1/
t
M_SCKO
I2S SCK frequency Master mode,
Supposing external
device response
delay is 30ns
7.8 9.2 MHz
f
S_SCKI
, 1/
t
S_SCKI
I2S SCK frequency Slave mode,
Supposing external
device response
delay is 30ns
12.8 13 MHz
d
S_SCKO
I2S SCK duty cycle Slave mode 50 50 %
t
M_FSOV
FS valid time Master mode 2.4 1.9 ns
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1040