Datasheet

...........continued
Name Description Mode VDD=1.8V VDD=3.3V Units
Min. Typ. Max Min. Typ. Max.
d
M_MCKO
I2S MCK duty cycle Master mode 45.4 50 45.4 50 %
d
M_MCKI
I2S MCK duty cycle Master mode, pin is
input (1b)
50 50 %
t
M_SCKOR
I2S SCK rise time
(3)
Master mode /
Capacitive load CL = 15
pF
9 4.6 ns
t
M_SCKOF
I2S SCK fall time
(3)
Master mode /
Capacitive load CL = 15
pF
9.7 4.5 ns
d
M_SCKO
I2S SCK duty cycle Master mode 45.6 50 45.6 50 %
f
M_SCKO
,1/
t
M_SCKO
I2S SCK frequency Master mode,Supposing
external device
response delay is 30ns
8 9.5 MHz
f
S_SCKI
,1/
t
S_SCKI
I2S SCK frequency Slave mode,Supposing
external device
response delay is 30ns
14.4 14.8 MHz
d
S_SCKO
I2S SCK duty cycle Slave mode 50 50 %
t
M_FSOV
FS valid time Master mode 4.1 4 ns
t
M_FSOH
FS hold time Master mode -0.9 -0.9 ns
t
S_FSIS
FS setup time Slave mode 2.3 1.5 ns
t
S_FSIH
FS hold time Slave mode 0 0 ns
t
M_SDIS
Data input setup
time
Master mode 34.7 24.5 ns
t
M_SDIH
Data input hold time Master mode -8.2 -8.2 ns
t
S_SDIS
Data input setup
time
Slave mode 4.6 3.9 ns
t
S_SDIH
Data input hold time Slave mode 1.2 1.2 ns
t
M_SDOV
Data output valid
time
Master transmitter 5.6 4.8 ns
t
M_SDOH
Data output hold
time
Master transmitter -0.5 -0.5 ns
t
S_SDOV
Data output valid
time
Slave transmitter 36.2 25.9 ns
t
S_SDOH
Data output hold
time
Slave transmitter 36 25.7 ns
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1039