Datasheet
37.16.5 I2S Timing
Figure 37-24. I2S Timing Master Mode
MCK output
SCK output
FS output
SD output
SD input
LSB right ch. MSB left ch.
t
M_SCKOR
t
M_SCKOF
t
M_SCKO
t
M_SDOH
t
M_FSOH
t
M_FSOV
t
M_SDOV
t
M_SDIH
t
M_SDIS
Master mode: SCK, FS and MCK are output
Figure 37-25. I2S Timing Slave Mode
Slave mode: SCK and FS are input
SCK input
FS input
SD output
SD input
LSB rignt ch. MSB left ch.
t
S_FSIH
t
S_SCKI
t
S_SDOH
t
S_FSIS
t
S_SDOV
t
S_SDIH
t
S_SDIS
Figure 37-26. I2S Timing PDM2 Mode
SCK input
SD input
PDM2 mode
Left Right
Left Right
Left
Right
t
PDM2RS
t
PDM2RH
t
PDM2LS
t
PDM2LH
Table 37-71. I2S Timing Characteristics and Requirements (Device Variant A)
Name Description Mode VDD=1.8V VDD=3.3V Units
Min. Typ. Max Min. Typ. Max.
t
M_MCKOR
I2S MCK rise time
(3)
Master mode /
Capacitive load CL = 15
pF
9.2 4.7 ns
t
M_MCKOF
I2S MCK fall time
(3)
Master mode /
Capacitive load CL = 15
pF
11.5 5.3 ns
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1038