Datasheet

37.16.4 SWD Timing
Figure 37-23. SWD Interface Signals
Stop Park Tri State
AcknowledgeTri State Tri State
Parity StartData Data
Stop Park Tri State
AcknowledgeTri State
Start
Read Cycle
Write Cycle
Tos
Thigh
Tlow
Tis
Data Data Parity Tri State
Tih
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
From debugger to
SWDIO pin
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Table 37-70. SWD Timings
(1)
Symbol Parameter Conditions Min. Max. Units
T
high
SWDCLK High period V
VDDIO
from 3.0 V to 3.6 V, maximum
external capacitor = 40 pF
10 500000 ns
T
low
SWDCLK Low period 10 500000
T
os
SWDIO output skew to
falling edge SWDCLK
-5 5
T
is
Input Setup time required
between SWDIO
4 -
T
ih
Input Hold time required
between SWDIO and
rising edge SWDCLK
1 -
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1037