Datasheet

Table 37-67. SPI Timing Characteristics and Requirements
(1)
Symbo
l
Parameter Conditions Min. Typ. Max. Units
t
SCK
SCK period Master 84 ns
t
SCKW
SCK high/low width Master - 0.5*t
SCK
-
t
SCKR
SCK rise time
(2)
Master - - -
t
SCKF
SCK fall time
(2)
Master - - -
t
MIS
MISO setup to SCK Master - 21 -
t
MIH
MISO hold after SCK Master - 13 -
t
MOS
MOSI setup SCK Master - t
SCK
/2 - 3 -
t
MOH
MOSI hold after SCK Master - 3 -
t
SSCK
Slave SCK Period Slave 1*t
CLK_APB
- -
t
SSCKW
SCK high/low width Slave 0.5*t
SSCK
- -
t
SSCKR
SCK rise time
(2)
Slave - - -
t
SSCKF
SCK fall time
(2)
Slave - - -
t
SIS
MOSI setup to SCK Slave t
SSCK
/2 - 9 - -
t
SIH
MOSI hold after SCK Slave t
SSCK
/2 - 3 - -
t
SSS
SS setup to SCK Slave PRELOADEN
=1
2*t
CLK_APB
+ t
SOS
- -
PRELOADEN
=0
t
SOS
+7 - -
t
SSH
SS hold after SCK Slave t
SIH
- 4 - -
t
SOS
MISO setup SCK Slave - t
SSCK
/2 -
18
-
t
SOH
MISO hold after SCK Slave - 18 -
t
SOSS
MISO setup after SS
low
Slave - 18 -
t
SOSH
MISO hold after SS
high
Slave - 10 -
Notes: 1. These values are based on simulation. These values are not covered by test limits in
production.
2. See 37.9 I/O Pin Characteristics
37.16.3 SERCOM in I
2
C Mode Timing
This section describes the requirements for devices connected to the I
2
C Interface Bus.
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1034