Datasheet

Table 37-64. GCLK_USB Clock Setup Recommendations

Clock setup USB Device USB Host

DFLL48M Open loop No No

Closed loop, any internal OSC source No No

Closed loop, any external XOSC source Yes No

Closed loop, USB SOF source (USB recovery mode)

(1)

Yes

(2)

N/A

FDPLL96M Any internal OSC source (32K, 8M, ... ) No No

Any external XOSC source (< 1MHz) Yes No

Any external XOSC source (> 1MHz) Yes

(3)

Yes

Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a

USB clock at +/-0.25% before 11ms after a resume.

2. Very high signal quality and crystal less. It is the best setup for USB Device mode.

3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external

OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up

time (See TDRSMDN in USB specification).

37.16 Timing Characteristics

37.16.1 External Reset

Table 37-65. External Reset Characteristics

Symbol Parameter Condition Min. Typ. Max. Units

EXT

Minimum reset pulse width 10 - - ns

Table 37-66. External Reset Characteristics (Silicon Revision G)

Symbol Parameter Condition Min. Typ. Max. Units

EXT

Minimum reset pulse width 1000 - - ns

SAM D21 Family

Electrical Characteristics

Datasheet Complete

DS40001882D-page 1032