Datasheet

...........continued
Symbol Parameter Conditions Min. Typ. Max. Units
t
LOCK
Lock time f
REF
= XTAL, 32 .768kHz, 100ppm
DFLLMUL = 1464
DFLLVAL.COARSE = DFLL48M
COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
100 200 500 μs
Table 37-54. DFLL48M Characteristics - Closed Loop Mode
(1)
(Device Variant B, C, D, and L)
Symbol Parameter Conditions Min. Typ. Max. Units
f
OUT
Average Output
frequency
f
REF
= 32 .768kHz 47.963 47.972 47.981 MHz
f
REF
Reference
frequency
0.732 32.768 33 kHz
Jitter Cycle to Cycle jitter f
REF
= 32 .768kHz - - 0.42 ns
I
DFLL
Power consumption
on V
DDIN
f
REF
=32 .768kHz - 403 453 μA
t
LOCK
Lock time f
REF
= 32 .768kHz
DFLLVAL.COARSE = DFLL48M
COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
- 200 500 μs
1. To insure that the device stays within the maximum allowed clock frequency, any reference clock
for DFLL in close loop must be within a 2% error accuracy.
SAM D21 Family
Electrical Characteristics
© 2018 Microchip Technology Inc.
Datasheet Complete
DS40001882D-page 1019